A self-aligned source process may be used generally for forming a source line of a semiconductor memory device. During the self-aligned source process, after a stack gate structure is formed, a cell region excluding a common source portion may be covered with a photosensitive film, a device separation film at a source line portion is removed by etching, and ion implantation is performed to form a common source line.
As illustrated in example FIGS. 1 and 2A, device separation film 12 may be formed at a device separation region on and/or oversemiconductor substrate 11. Tunnel oxide film 13 and first polysilicon film 14 may be sequentially formed on and/or over the entire structure and then patterned by a lithography process and an etching process with a floating gate mask, thereby forming a floating gate.
Dielectric film 15, second polysilicon film 16, tungsten silicide film 17, and oxide film 18 may then be sequentially formed on and/or over the entire structure and then patterned by a lithography process and an etching process with a control gate mask, thereby forming a control gate. Therefore, stack gate structure 20 in which a floating gate and a control gate are laminated may be formed. Photosensitive film 19 may then be formed over the entire structure and then patterned by an exposure process and a development process with a self-aligned source mask, such that the source portion is exposed.
As illustrated in example FIGS. 1 and 2B, exposed device separation film 12 at the source line portion may then be removed by a self-aligned source (SAS) etching process, thereby exposing semiconductor substrate 11 at the source line portion. After the self-aligned source etching process is completed, a curing process may be performed. A cell source ion implantation process may be performed with patterned photosensitive film 19 as an ion implantation mask. Then, impurity ions may be implanted into semiconductor substrate 11 at the source line portion, thereby forming common source line 21.
As illustrated in example FIGS. 1 and 2C, the entire cell array may then be exposed and an impurity ion implantation process is performed, thereby forming drain region 22.
As illustrated in example FIGS. 1 and 2D, an insulating film may then be formed on and/or over the entire structure and an entire surface etching process is then performed, thereby forming spacer 23 on each sidewall of stack gate structure 20.
In such a structure, since multiple cells are connected to a single source line, i.e., the common source line is used, source resistance may be large. Accordingly, a cell current characteristic may be deteriorated.